The Memory Race Behind AI Computing

Conventional DRAM and high-bandwidth memory serve different roles in AI computing systems. Editorial conceptual illustration supplied by the owner, not a precise physical layout or a vendor product photograph.

AI processors need memory that can hold and deliver data fast enough. Explore how DRAM, HBM, advanced packaging and competition among memory manufacturers affect AI computing and its cost.

An AI processor depends on the memory feeding it

An AI accelerator does its work on data, and that data has to come from somewhere. Memory holds the data the processor works on, and it has to deliver that data quickly enough to keep the processor busy. When memory cannot keep up, the processor waits.

Two properties matter. Capacity is how much data the memory can hold. Bandwidth is how much data it can move per second, and SK hynix describes it for high-bandwidth memory as the total data capacity that one memory package can process per second.

This is why memory has become a topic of its own in AI infrastructure. A faster processor does little good if the memory next to it cannot supply data at the same pace, and the best memory is no use if too little of it can be manufactured.

Conventional DRAM and HBM do different jobs

Conventional DRAM is the memory most computing systems have long used. In servers it usually comes as modules such as RDIMMs, and TrendForce reports that cloud providers and server makers are buying more bits to meet RDIMM demand for general servers supporting agentic AI workloads (TrendForce, 30 September 2026).

High-bandwidth memory, or HBM, is built differently. SK hynix describes it as vertically interconnecting multiple DRAM chips, which dramatically increases data processing speed compared with conventional DRAM, and Micron calls it 3D-stacked DRAM designed for AI, high-performance computing and data-intensive workloads. SK hynix counts HBM4 as the sixth generation, after the original HBM, HBM2, HBM2E, HBM3 and HBM3E.

Conventional DRAM and HBM compared on what the sources report
Aspect	Conventional DRAM	HBM
Construction	DRAM chips on modules such as server RDIMMs	Several DRAM dies stacked and interconnected, with one base die per stack
Where it appears in AI systems	Main memory in general-purpose servers, including those running agentic AI workloads	Memory attached to AI accelerators, built for very high data throughput
What limits supply	Advanced-process and wafer capacity	The same advanced-process and wafer capacity, with yields and output of next-generation products still ramping
Cost pattern	Contract prices that TrendForce projects to rise in 4Q26	A base die per stack, so cost does not fall in proportion to the number of layers

The two are not separate worlds. TrendForce reports that continued growth in AI server demand keeps HBM and conventional DRAM in competition for limited advanced-process and wafer capacity. Sources: TrendForce, 29 September 2026, TrendForce, 30 September 2026, SK hynix and Micron.

HBM4 raises the numbers, according to the manufacturers

The headline change in HBM4 is a wider interface. SK hynix says it doubled the number of I/O terminals from the previous generation to 2,048, and Samsung describes the same move from 1,024 to 2,048 pins. A wider interface and a higher speed per pin both raise the data a stack can move.

Pin speed is the second lever. The JEDEC standard operating speed for HBM4 is 8 Gbps per pin, and each manufacturer reports operating above it. Multiplying pins by speed and dividing by eight gives a theoretical peak per stack, which is the arithmetic the figures below follow.

What pin speed means for one HBM4 stack

Select a pin speed to see the theoretical peak bandwidth of one stack with a 2,048-pin interface.

8 Gbps

8 Gbps (selected)2.05 TB/s

10 Gbps2.56 TB/s

11.7 Gbps3.00 TB/s

13 Gbps3.33 TB/s

TechiesJournal arithmetic: 2,048 × 8 Gbps ÷ 8 = 2.05 TB/s

The JEDEC standard operating speed for HBM4, which SK hynix identifies and which Samsung calls the industry standard. The manufacturers report running above it.

A theoretical peak per stack from the interface width and the pin speed. It is not the throughput of a whole system, and the figures are the manufacturers’ own.

Theoretical peak per stack, by pin speed:

8 Gbps: 2,048 × 8 Gbps ÷ 8 = 2.05 TB/s. The JEDEC standard operating speed for HBM4, which SK hynix identifies and which Samsung calls the industry standard. The manufacturers report running above it.

Over 10 Gbps: 2,048 × 10 Gbps ÷ 8 = 2.56 TB/s. SK hynix reports operating speeds over 10 Gbps in its HBM4 and gives no bandwidth figure. This row uses 10 Gbps as a floor, so the real figure is higher.

11.7 Gbps: 2,048 × 11.7 Gbps ÷ 8 = 3.00 TB/s. Samsung reports a consistent 11.7 Gbps. Micron reports over 11 Gb/s and more than 2.8 TB/s, which fits the same arithmetic.

13 Gbps: 2,048 × 13 Gbps ÷ 8 = 3.33 TB/s. Samsung says its HBM4 can be taken up to 13 Gbps, for a maximum of 3.3 TB/s per stack, which matches this result.

The three manufacturers describe their HBM4 in different ways, at different dates and with different test bases. The table collects what each reported, and it is a record of claims, not a benchmark.

HBM4 as each manufacturer reports it, with different stages, dates and test bases
Company	Stage reported	Pin speed	Bandwidth per stack	Power efficiency claim and its stated baseline
SK hynix	Development complete and mass-production system readied, 12 September 2025	Over 10 Gbps	Doubled from the previous generation	Improved by more than 40%, no baseline stated in the release
Samsung	Mass production begun and commercial shipments, 12 February 2026	11.7 Gbps, up to 13 Gbps	Up to 3.3 TB/s	40% better than HBM3E
Micron	High-volume production of 36 GB 12-high HBM4, per its product page	Over 11 Gb/s	More than 2.8 TB/s, from Micron’s internal testing	More than 20% better than HBM3E

Capacity follows the number of stacked layers. Samsung offers HBM4 from 24 GB to 36 GB with 12-layer stacking and plans 16-layer stacking for up to 48 GB, while Micron’s product page lists a 36 GB 12-high stack. SK hynix also says it expects up to 69% better AI service performance from its HBM4, a company projection that depends on the system around it.

Because the stage, the date and the test basis differ, the three rows should not be ranked against one another. The useful comparison is the one a buyer would make with a specific accelerator, at a specific stack height, under a specific workload. Sources: SK hynix, 12 September 2025, Samsung, 12 February 2026 and Micron.

Supply and cost shape what gets built

Memory is not only a performance question. TrendForce expects HBM to stay supply-constrained through 2027, and it has raised its 2027 HBM price outlook, projecting that the blended average selling price will rise 121% year on year. These are forecasts, and they depend on yields, output and demand that can change.

One response is to change how much HBM each accelerator carries. TrendForce reports that GPU and ASIC makers are considering 8-high stacks in place of earlier plans for 12-high ones, driven by limited supply and rising system costs, not by weaker demand. Fewer layers lower the cost per stack and let the same HBM output serve more accelerators.

Why an 8-high stack is not cheaper per gigabit

Switch between a 12-high and an 8-high HBM stack to see what is shared and what is not.

12-high stack

DRAM layer 12

DRAM layer 11

DRAM layer 10

DRAM layer 9

DRAM layer 8

DRAM layer 7

DRAM layer 6

DRAM layer 5

DRAM layer 4

DRAM layer 3

DRAM layer 2

DRAM layer 1

Base die (one per stack)

Twelve DRAM layers share the cost of one base die. TrendForce says earlier plans for many GPUs and ASICs assumed this height.

A simplified drawing of TrendForce’s explanation, not a cost model. The only numbers are TrendForce’s forecast.

The two stack heights:

12-high stack: Twelve DRAM layers share the cost of one base die. TrendForce says earlier plans for many GPUs and ASICs assumed this height.

8-high stack: Eight layers lower the cost per stack and the accelerator’s overall bill of materials. The base die cost does not fall in proportion, so the cost per gigabit is higher. TrendForce expects a premium of roughly 10 to 20% per gigabit in 2027, a forecast.

Fewer layers do not make memory cheaper per gigabit, though. Each HBM stack needs one base die whose cost does not fall in proportion to the number of DRAM layers, so an 8-high stack spreads that cost over less capacity. TrendForce expects 8-high products to carry a premium of roughly 10 to 20% per gigabit over 12-high products in 2027, and it does not expect capacity cuts to reverse the broader trend of HBM price increases.

Conventional DRAM feels the same pressure. TrendForce projects conventional DRAM contract prices to rise 10 to 15% quarter on quarter in 4Q26, says suppliers continue to prioritise advanced-process capacity for high-performance server products, and expects server DRAM to remain undersupplied in 4Q26. It names component supply, packaging and testing capacity, and front-end production flexibility among the constraints. It also says PC DRAM supply could decline in 2027 as more capacity shifts to servers. Sources: TrendForce, 29 September 2026 and TrendForce, 30 September 2026.

CXMT’s announcement concerns conventional DRAM, not HBM4

The memory race is not limited to the three manufacturers above. On 20 September 2026, CXMT announced mass production of its fifth-generation DRAM technology platform, which it calls G5, at the 2026 World Manufacturing Convention in Hefei (CXMT, 20 September 2026).

CXMT says G5 reaches an active-area half-pitch of 11.95 nm and at least 50% more die per wafer than its previous platform, normalised to an 8 Gb density baseline, and that it is closing the gap with what it calls the world’s most advanced volume-production memory platforms. The first products it named are two LPDDR5X parts with 24 Gb per die, aimed at smartphones and portable consumer electronics, and it says they are already in mass production.

That is an announcement about conventional low-power DRAM for consumer devices. It says nothing about HBM4, and a stronger position in conventional DRAM is not evidence that CXMT is producing HBM at commercial scale. The distinction matters, and in TechiesJournal’s reading it is also why the announcement still deserves attention, because TrendForce reports that HBM and conventional DRAM compete for limited advanced-process and wafer capacity.

What this means for people planning AI infrastructure

This section is TechiesJournal’s reading of the sources, not a recommendation from any manufacturer. The practical points follow from what the sources report.

Ask for the memory configuration, not only the processor name. HBM generation, stack height, capacity per accelerator and the memory vendor all affect what a system delivers and what it costs.
Compare vendor figures on the same basis. Pin speed, stack height, test conditions and production stage differ between announcements, and a theoretical stack bandwidth is not the throughput of a whole system.
Plan for tight supply and rising prices. TrendForce’s outlook runs through 2027, but forecasts change, so build in room for revision.
Do not forget conventional server memory. General-purpose servers, including those running agentic AI workloads, use conventional DRAM modules, and TrendForce expects server DRAM to stay undersupplied in 4Q26.
Treat announcements as announcements. A development milestone, a first shipment and high-volume production are different stages, and each source in this article says which one it means.

The memory race is a question of who can make enough of the right memory, stack it, package it and deliver it on time. For anyone buying or building AI capacity, that now shapes cost and availability as much as the processor does.

Go deeper

Sources reviewed October 21, 2026. Manufacturer figures are company-reported and market figures are forecasts. No independent benchmark is claimed.

Manufacturer announcements

SK hynix, Completes World’s First HBM4 Development and Readies Mass Production, September 12, 2025, development completion and mass-production readiness.
Samsung, Ships Industry-First Commercial HBM4, February 12, 2026, company-reported shipments and specifications.
Micron, High-bandwidth memory (HBM), product portfolio and current product-stage descriptions.
CXMT, Announces Mass Production of 5th-Generation DRAM Technology Platform, September 20, 2026, conventional DRAM and LPDDR5X.

Market research

TrendForce, HBM Supply Constraints Persist, 2027 Price Outlook Revised Upward, September 29, 2026, forecasts.
TrendForce, AI Server Demand Sustains Memory Contract Price Increases in 4Q26, September 30, 2026, forecasts.